The VME1553-1 is a low cost interface between a dual redundant MIL-STD-1553B databus and the VMEbus. Through software the VME1553-1 may be configured to operate as a 1553 Bus Controller (BC), Remote Terminal (RT), or Bus Monitor (BM). The VME1553-1 contains all the functions necessary to handle the MIL-STD-1553B protocol including mode codes, broadcast, and RT-to-RT transfers. Protocol functions, such as Manchester encoding and decoding, address recognition, word count, and word and message validation are handled automatically without intervention by the host computer. Data are passed via an on-board buffer memory. Memory mapped control and status registers are used by the host computer to configure the VME1553-1 and to read its status.
Commercial grade components and programmable devices have been used in the design of the VME1553-1 to make it an economical MIL-STD-1553B interface while maintaining a high level of functionality. The complete interface is housed on a standard double height (6U size) VMEbus module. The normal configuration includes the MIL-STD-1553 transceivers, but provisions exist for other signal characteristics such as MIL-STD-1773 (fiber optic), MACAIR, or RS-485. The VME1553-1 is designed for development, production, and testing of products with a MIL-STD-1553 interface. It is especially useful in running functional tests. It can run all protocol tests that do not require error generation.
Command and data words are loaded by the host computer (VME master) into the buffer memory on the VME1553-1. Thirty-two messages may be preloaded. The host indicates which message to transmit by setting a control register write or an external trigger pulse. The status word and data word response are read from the buffer memory. A message may be repeatedly triggered without host intervention.
Enabling the simulate feature causes the bus controller to transmit the complete message including a simulation of the RT response with proper gaps. For RT-to-RT transfers either one or both of the RTs may be simulated.
The host computer configures the VME1553-1 to operate as the remote terminal by setting the mode and terminal address. Whenever a valid command word with the correct terminal address or broadcast address is received on either bus, the VME1553-1 responds in accordance with MIL-STD-1553B. The associated data are mapped to/from a 32 word block in the buffer memory according to the TR bit and subaddress of the command word. A data word associated with a mode code is mapped to a separate mode code block. Enabling the WRAP feature causes data received by subaddress 30 to be transmitted from subaddress 30. The Service Request, Busy, Subsystem Flag and Terminal Flag bits may be set or cleared by the host. The Autobusy feature can be enabled, so that the Busy bit is automatically set after receiving a message. The Busy bit may then be cleared by the host after processing the message.
In RT Monitor Mode the VME1553-1 monitors all messages to and from a specified terminal address. At any given time the buffer memory holds the most recent data words for each TR bit and subaddress combination and the most recent command and status words to or from the specified RT.
The VME1553-1 is a VMEbus slave and interrupter (i.e., it can respond to accesses from a master and can initiate an interrupt). A switch selects either standard (24-bit) or short (16-bit) addressing from the VMEbus. The VMEbus memory address space of 8K bytes is evenly divided between registers and memory. The byte wide registers are accessed at odd locations starting at the bottom of the address space, using D08(O) transfers. The upper half of the address space is allocated to the 4K bytes of dual port memory and is accessed two bytes at a time, using D16 transfers.
When enabled, an interrupt is initiated on the VMEbus after the processing of a message has been completed (after an error, no response, or completed message). A jumper and a switch are used to select one of the seven VMEbus interrupt request lines. The value in the Status/ID register is returned as a single byte interrupt acknowledge.